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Hardware architecture
Yiffware hardware architecture manuals
YiffCore
A RISC-like SoC architecture for gay critters
General architecture
Provides a general architectural overview
Introduction
YiffCore is a 64-bit System-on-Chip architecture targeting low-power embedded systems within the scope of Yiffware infrastructure. YiffCore utilizes 32-bit fixed-width instructions and a handful of registers used to perform data operations. The bus in-use is t...
Mandatory access control (MAC)
YiffCore is a tri-MAC (mandatory access control) architecture, in other words, the privilege levels are divided into three rings: 0, 1, and 2. Where 0 is the most privileged and is one-level below the operating system kernel, 1 is reserved for the operating sy...
Processor registers
YiffCore utilizes 32 general-purpose registers for various data movement operations, to differentiate between temporaries and other registers, the temporaries are known as CUM stores (the SoC has many holes :3): ZR : Fixed to zero, writes are igno...
Instruction set architecture
This chapter describes the instruction set architecture of YiffCore
Instruction listing
Below are the instructions available to the programmer: MNEMONIC OPCODE BRIEF --------------------------------------------------------------------------------------- NOP 0x00 No-operat...
Processor reset state
Upon power-up and/or assertion of the RESET# line, the processor is to enter a reset state in which all registers besides IP, SP, FP, TP, GP and ZP (which are initialized to zero) are to be initialized to a value of 0x1A1A1A1A1A1A1A1A. The instruction pointer ...